1. Field
This disclosure relates generally to semiconductor manufacturing, and more specifically, to the making of NVM cells.
2. Related Art
Non-volatile memories (NVMs), which are a major portion of the semiconductor industry, are often found on integrated circuits that have one or more processing units. One of the characteristics of NVM cells is that writing cells includes both erasing and programming. Both of these operations typically require higher voltages, commonly significantly higher, than are required for general purpose circuits such as the logic transistors used for providing a processing unit. Also, both programming and erasing require significantly more time than reading. Thus, there is the continuing effort to reduce the voltages required for programming and erase and reduce the time for performing those functions. In the case of erasing, which is typically removing electrons from a storage layer. In the case of nanocrystals being used for the storage layer, this is achieved using tunneling and that is most commonly done using top erase in which electrons tunnel from the nanocrystals to the overlying control gate.
For the erase then, a sufficiently high voltage must be applied to the control gate to achieve the tunneling. An issue though is that eventually electrons can tunnel from the substrate under the nanocrystals to the nanocrystals counteracting the tunneling from the top side. Eventually an equilibrium can be reached in which the rate of tunneling from the substrate to the nanocrystals equals the rate of tunneling from the nanocrystals to the control gate and in effect, there is no further erasing occurring because there is no net loss of electrons in the nanocrystals. This acts to limit the erase and also increase the time to erases.
Accordingly there is a need to provide further improvement in one or more of the issues raised above.